Design of Energy-Efficient Application-Specific Set Processors / (Record no. 26177)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03746cam a22002414a 4500 |
| 001 - CONTROL NUMBER | |
| control field | vtls000002486 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | VRT |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20250102225208.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 081129s2004 maua |b 000 0 eng |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 1402077300 (alk. paper) |
| 039 #9 - LEVEL OF BIBLIOGRAPHIC CONTROL AND CODING DETAIL [OBSOLETE] | |
| Level of rules in bibliographic description | 201402040100 |
| Level of effort used to assign nonsubject heading access points | VLOAD |
| Level of effort used to assign subject headings | 201006271018 |
| Level of effort used to assign classification | malmash |
| Level of effort used to assign subject headings | 200812011519 |
| Level of effort used to assign classification | venkatrajand |
| Level of effort used to assign subject headings | 200811291427 |
| Level of effort used to assign classification | Noora |
| -- | 200811291425 |
| -- | Noora |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.9.A73 |
| Item number | G56 2004 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Glokler, Tilman. |
| 9 (RLIN) | 54092 |
| 245 10 - TITLE STATEMENT | |
| Title | Design of Energy-Efficient Application-Specific Set Processors / |
| Statement of responsibility, etc. | by Tilman Glökler and Heinrich Meyr. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Boston : |
| Name of publisher, distributor, etc. | Kluwer Academic, |
| Date of publication, distribution, etc. | 2004. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xx, 234 p. : |
| Other physical details | ill. ; |
| Dimensions | 25 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references (p. [221]-234) |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Foreword. Acknowledgements. About the Authors. I: Introduction. 2: Focus and Related Work. 2.1. Focus of this Work. 2.2. Previous Work. 2.3. Differences to Previous Work. 3: Efficient Low-Power Hardware Design. 3.1. Metrics of the Implementation and the Hardware Design Methodology. 3.2. Basics of Low-Energy Hardware Design. 3.3. Techniques to Reduce the Energy Consumption. 3.4. Concluding Remarks. 4: Application-Specific Processor Architectures. 4.1. Definitions of ASIP Related Terms. 4.2. ASIP Applications. 4.3. ASIP Design Space. 4.4. Critical Factors for Energy-Efficient ASIPs. 4.5. Concluding Remarks. 5: The ASIP Design Flow. 5.1. Example Applications. 5.2. Application Profiling and Partitioning. 5.3. Combined ASIP HW/SW Synthesis and Profiling. 5.4. Verification. 5.5. Concluding Remarks. 6: The ASIP Design Environment. 6.1. The LISA Language. 6.2. The LISA Design Environment. 6.3. Extensions to the LISA Design Environment. 6.4. Concluding Remarks. 7: Case Studies. 7.1. Case Study I: BVD-T Acquisition and Tracking. 7.2. Case Study II: Linear Algebra Kernels and Eigenvalue Decomposition. 7.3. Concluding Remarks. 8: Summary. A: ASIP Development Using LISA 2.0. A.1. The LISA 2.0 Language. A.2. Design Space Exploration. A.3. Design Implementation. A.4. Software Tools Generation. A.5. System Integration. A.6. Summary. B: Computational Kernels. B.1. The CORDIC Algorithm. B.2. FIR Filter. B.3. The Fast Fourier Transform. B.4. Vector/Matrix Operations. B.5. Complex EVD Using a Jacobi-like Algorithm. C: ICORE Instruction Set Architecture. C.1. Processor Resources. C.2. Pipeline Organization. C.3. Instruction Summary. C.4. Exceptions to the Hidden Pipeline Model. C.5. ICORE Memory Organization and I/O Space. C.6. Instruction Coding. D: Different ICORE Pipeline Organizations. E: ICORE HDL Description Templates. E.1. Generic Register File Entity. E.2. Generic Bit-Manipulation Unit. F: Area, Power and Design Time for ICORE. G: Acronyms. Bibliography. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | After a brief introduction to low-power VLSI design, the design space of ASIP instruction set architectures (ISAs) is introduced with a special focus on important features for digital signal processing. Based on the degrees of freedom offered by this design space, a consistent ASIP design flow is proposed: this design flow starts with a given application and uses incremental optimization of the ASIP hardware, of ASIP coprocessors and of the ASIP software by using a top-down approach and by applying application-specific modifications on all levels of design hierarchy. A broad range of real-world signal processing applications serves as vehicle to illustrate each design decision and provides a hands-on approach to ASIP design. Finally, two complete case studies demonstrate the feasibility and the efficiency of the proposed methodology and quantitatively evaluate the benefits of ASIPs in an industrial context. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer architecture. |
| 9 (RLIN) | 868 |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Meyr, Heinrich. |
| 9 (RLIN) | 54093 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Library of Congress Classification |
| Suppress in OPAC | No |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total checkouts | Full call number | Barcode | Date last seen | Copy number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Library of Congress Classification | Library | Library | First Floor | 21/12/2024 | QA76.9.A73 G56 2004 | 7913 | 21/12/2024 | 1 | 21/12/2024 | Books |